1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to an apparatus for performing both multiplication and addition. Still more particularly, the present invention relates to a low latency fused multiply-adder.
2. Description of the Prior Art
Fused multiply-adders combine a multiplication operation with an add operation. Within a fused multiply-adder, a multiplicand and a multiplier are initially multiplied via a partial product generation module. The partial products are then added by a partial product reduction module that reduces the partial products to a Sum and a Carry in their redundant form. The redundant Sum and Carry are further added to an addend via a carry-save adder to form another redundant Sum and Carry. The second redundant Sum and the second redundant Carry are subsequently added within a carry-propagate adder to yield a Sum Total.
While a prior art multiply-add operation performed by a fused multiply-adder typically has a lower latency than the combined latencies of individual multiplication operation and addition operations, the present invention recognizes that the configuration of a prior art fused multiply-adder contributes to an increase in the latency of multiplication operations. Consequently, it would be desirable to provide an improved fused multiply-adder with a low latency multiplication operation.